This invention relates in general to packet exchange systems adapted to perform routing assignment for data packet strings of fixed-length packets and more particularly to a high speed packet exchange method and system suitable for exchange of information from multimedia having various bit rates ranging from several bits per second to several of hundreds of M bits per second.
This type of packet exchange system is described in, for example, JP-A-No. 59-135994 entitled "TDM Switching System". In this exchange system, a packet is a data block having a fixed length of N bytes (for example, N=16), of which the initial one byte is representative of a logical channel number for discriminating packets in a multiplexed signal from each other and the following 15 bytes carry information to be transferred to a destination station.
Essentially, the function of the exchange for packets is to assign individual arriving packets, identified by line numbers each transmitting a multiplexed signal carrying information and packet logical channel numbers, with new identifications. The new identification signifies conversion between two attributes of the same kind, i.e., conversion of a packet (s, i) into a packet (t, j), where s is a line number transmitting an incoming multiplexed signal, i is a header, t is a line number transmitting an outgoing multiplexed signal, and j is a new header.
A packet exchange system having the above function will be described with reference to FIG. 2. A packet inputted to the exchange through a multiplex line a, b, . . . or m has a format as shown in FIG. 3A. In the format, an input logical channel number IL corresponds to the aforementioned header i, control information CTL represents either check information for checking errors in the contents of the packet or information indicative of the kind of services applied to the packet, and data DA is information to be transferred to a destination station. Depending on the type of packet, the control information may be omitted.
When one of input control circuits 1a to 1m, assumed to be 1s herein, receives a packet, this input control circuit 1s derives an input logical channel number IL from the received packet, prepares a pair of an input line number IC indicative of the number assigned to a multiplex line s through which the packet is inputted and the IL, and sends to a table management unit 2 a signal S4 indicative of the pair having a format as shown in FIG. 3D. The table management unit 2 includes a routing control table 21 and a table access circuit 22. Stored in the routing control table 21 at an address AT determined, in respect of each call, from the input line number IC and input logical channel number IL are a set of output line number OC and output logical channel number OL. According to the prior art system, the information has been written in the routing control table 21 under the control of a call control processor 6 simultaneously with setting of a call. On the basis of the input line number IC and input logical channel number IL sent from the input control circuit 1s , the table access circuit 22 determines the address TA on routing control table 21 on which exist the output line number OC and output logical channel number OL for a call to which the packet belongs, reads from the routing control table 21 the output line number OC and output logical channel number OL and returns them to the input control circuit 1s.
When receiving the output line number OC and output logical channel number OL, the input control circuit 1s adds this information to data DA, updates the contents of control information CTL present in the received packet as desired or required and thereafter sends the received packet to a packet switch 4. The packet switch 4 sends the received packet from the input control circuit 1s to an output control circuit 5t (desired one of output control circuits 5a to 5n). The output control circuit 5t removes the output line number OC from the packet and delivers to one of output lines a' to n', represented by t' herein, a packet S3 having a format as shown in FIG. 3C.
The above-described prior art system does not perform flow control of packet between one exchange and another or between a terminal device and the exchange and therefore many packets are permitted to arrive at the exchange at a time. If the number of packets arriving at the exchange exceeds the number of packets which can be retained in the exchange, then congestion will occur and an event that many packets in excess of a treatable number are forced to be discarded will occur at a certain probability.
U.S. patent application Ser. No. 07/218,217 filed on July 13, 1988 and assigned to the same assignee also pertains to a packet exchange system.